Method of forming a high voltage device

ABSTRACT

A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask is formed on the substrate with an opening exposing a portion of a top gate stack layers. Ions are implanted through the opening and gate stack layers into the substrate to form a channel well. The substrate is patterned to at least remove portion of a top gate stack layer unprotected by the implant mask.

BACKGROUND

Lateral Double-Diffused (LD) transistors have been widely employed inhigh voltage applications. For high performance LD transistors, lowdrain-to-source on-resistance (Rds_(on)) is desired to minimize itspower dissipation when it is turned on, as well as high breakdownvoltage to maximize its voltage capability. To achieve low Rds_(on), thechannel of the high LD transistor should be as short as possible.

As technology evolves into era of deep sub-micron (e.g., beyond 0.35 μm)Very-Large-Scale Integration (VLSI), there is a desire for both highvoltage (HV) LD transistors and low voltage (LV) transistors to befabricated on the same substrate. Generally, the processes for formingLV devices, such as complementary metal-oxide-semiconductor (CMOS)processes, are used to form the HV devices. However, conventional CMOSprocesses are incompatible for forming HV transistors. For example,process overlay issues make it difficult for alignment of the HV channelwell, which defines the channel length. Process variations in processoverlay requires large process windows. This makes forming short channellengths to achieve low RDs_(on) difficult if not impossible.Furthermore, the thin gate electrodes used prevent them serving as ahard mask, further exacerbating process control in forming the channelwell.

From the foregoing discussion, it is desirable to provide reliable HVdevices formed with short channel lengths to have low Rds_(on).

SUMMARY

A method of forming a device is presented. The method includes providinga substrate prepared with an active device region. The active deviceregion includes gate stack layers of a gate stack comprising at least agate electrode layer over a gate dielectric layer. An implant mask isformed on the substrate with an opening exposing a portion of a top gatestack layers. Ions are implanted through the opening and gate stacklayers into the substrate to form a channel well. The substrate ispatterned to at least remove portion of a top gate stack layerunprotected by the implant mask.

In another embodiment, a device is disclosed. The device includes asubstrate prepared with an active region. The active region includes agate stack with a gate electrode layer over a gate dielectric layer. Afirst edge of a gate and a second edge of the gate are patternedseparately. A doped channel well is disposed in the substrate adjacentto the first edge of the gate. The first edge of the gate overlaps thechannel well with a channel edge of the channel well beneath the gate.The first edge of the gate and the channel edge define an effectivelength of the device. A doped drift well is adjacent to the second edgeof the gate.

These and other objects, along with advantages and features of thepresent invention herein disclosed, will become apparent throughreference to the following description and the accompanying drawings.Furthermore, it is to be understood that the features of the variousembodiments described herein are not mutually exclusive and can exist invarious combinations and permutations.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the sameparts throughout the different views. Also, the drawings are notnecessarily to scale, emphasis instead generally being placed uponillustrating the principles of the invention. In the followingdescription, various embodiments of the present invention are describedwith reference to the following drawings, in which:

FIG. 1 shows an embodiment of a device;

FIGS. 2 a-g show an embodiment of a process for forming a device; and

FIGS. 3 a-g show an alternative embodiment of a process for forming adevice.

DETAILED DESCRIPTION

Embodiments generally relate to semiconductor devices or integratedcircuits. More particularly, some embodiments relate to high powerdevices. For example, high power devices include lateral double-diffused(LD) transistors, such as metal oxide transistors (MOS). The high powerdevices can be employed as switching voltage regulators for powermanagement applications. The LD transistors can be easily integratedinto devices or ICs. The devices or ICs can be incorporated into or usedwith, for example, consumer electronic products, particularly portableconsumer products, such as cell phones, laptop computers and personaldigital assistants (PDAs).

FIG. 1 shows a portion 100 of an embodiment of a device. As shown, theportion includes a substrate 101. The substrate, for example, comprisesa silicon substrate. The substrate can be lightly doped with p-typedopants. N-type or other types of substrates, such as silicon germaniumor silicon-on-insulator (SOI), are also useful.

The substrate may be prepared with first and second regions 110 and 160.In one embodiment, the first region comprises a low voltage (LV) deviceregion while the second region comprises a high voltage (HV) deviceregion. The regions may be other types of device regions or additionaldevice regions may be provided. For example, a dual gate oxide (DGO)region may be provided for DGO devices. The DGO devices may be used forI/O circuitries. Alternatively, the device may include only a HV region.

The first region, in one embodiment, comprises first and second typeactive sub-regions 112 and 116. The first and second types arecomplementary types, forming a complementary type device. For example,the complementary type device comprises a complementary metal oxidesemiconductor (CMOS) device. Forming non-complementary or other types ofdevices is also useful.

The first type active sub-region, for example, comprises a n-type activesub-region and the second type active sub-region comprises a p-typeactive region. The first type active sub-region comprises a second typedoped well 122; the second type active sub-region comprises a first typedoped well 124. For example, the first type active sub-region comprisesa p-type doped well and the second type active sub-region comprises an-type doped well. Other configurations of active sub-regions are alsouseful. P-type dopants can include boron (B), indium (In) or acombination thereof while n-type dopants can include phosphorus (P),arsenic (As), antimony (Sb) or a combination thereof.

A first type transistor 140 is provided in the first type activesub-region and a second type transistor 150 is provided in the secondtype active sub-region. For example, a n-type transistor is provided inthe n-type active sub-region with a p-type doped well while a p-typetransistor is provided in the p-type active sub-region with a n-typedoped well. The transistors, in one embodiment, are MOS field effecttransistors (MOSFETs). Other types of transistors may also be useful.

A transistor, for example, comprises a gate having a gate electrode 144over a gate dielectric 142. The gate electrode, for example, comprisespolysilicon. Other types of gate electrode materials, such aspolysilicide or metal silicide, are also useful. Polysilicide or metalsilicide gates can be formed by reacting the desired metal withpolysilicon. Various types of metal, such as cobalt, titanium or nickel,can be used. Other types of gate electrode materials may also be useful.Furthermore, the gate electrode may be doped with dopants. Doping thegate electrode may depend on the technology. The gate electrode, forexample, may be doped with the same dopant type of the transistor type.Doping the gate electrode with other dapant types is also useful. Thegate dielectric can be silicon oxide. Other types of gate electrode orgate dielectric materials can also be useful. The material of the gateelectrode and gate dielectric may depend on the technology. For example,cobalt silicide gate electrodes may be used for 0.18 μm and 0.13 μmtechnologies while nickel silicide may be used for 0.09 μm technologies.Other configurations of gate electrode and gate dielectric materials arealso useful.

Sidewalls of the gate can be provided with sidewall spacers 148. Thesidewall spacers, for example, comprise a dielectric material, such assilicon oxide, silicon nitride or a combination thereof. Other types ofmaterials can be used for the sidewall spacers.

Adjacent to the gate are diffusion regions 146. The diffusion regionsserve as, for example, source and drain of the transistor. Extensiondiffusion regions 147 can be provided. The extension diffusion regions,for example, are shallow diffusion regions which extend under thespacers. The diffusion regions (including the extension diffusionregions) of the first type transistor are doped with the first typedopants and the diffusion regions of the second type transistor aredoped with the second type dopants. For example p-type diffusion regionsare provided for p-type transistors and n-type diffusion regions areprovided for n-type transistors. The depth and dopant concentration ofthe diffusion regions may depend, for example, on the application, suchas voltage requirements.

The HV region includes a HV active region 165. In one embodiment, the HVactive region comprises a first type active region. For example, the HVactive region comprises a n-type active region. Providing a p-type HVactive region is also useful. Furthermore, it is understood that the HVregion is depicted with only one active region for purpose ofsimplification and that the HV region can include numerous HV activeregions or sub-regions. For example, the HV active sub-regions can becomplementary types of HV sub-regions for complementary types of HVdevices.

Isolation regions 180, such as shallow trench isolation (STI) regionsare provided to isolate the LV and HV regions as well as activesub-regions within the regions. Other types of isolation regions arealso useful.

In one embodiment, the first type HV active region comprises at leastfirst and second portions. The first portion comprises a second type HVchannel (or body) well 135 and the second portion comprises a first typeHV drift well 136. The HV drift well, for example, defines the type ofHV device. For example, a p-type HV active region would have a n-type HVchannel well and a p-type HV drift well. In one embodiment, a third ormiddle portion separates the channel and drift wells. In otherembodiments, the first and second portions are contiguous portions. Forexample, the HV channel and HV drift wells contact each other.

A deep well 132 may be provided in the HV active region, encompassingthe HV channel and drift wells. Generally, the deep well comprisesdopants of the first type or same as the HV device type. The deep wellmay be used to isolate the drift well from the substrate. For example, ap-type device will have a n-type deep well. In some cases, the deep wellcan be optional or the deep well can comprise dopants of the second oropposite type of the HV device type. For example, in the case of an-type HV device, the deep well can be a p-type or n-type deep well. Thedifferent types of deep well selected may depend on the type ofsubstrate. Generally, p-type doped substrates are used for fabricatingdevices. When p-type substrates are used, the n-type deep well may beoptional. This is because the n-type drift well is already differentfrom the p-type substrate. For a n-type substrate, a p-type deep wellmay be used to isolate the channel well from the substrate. Otherconfigurations of deep wells may also be useful.

As shown, a first type HV device is provided in the first type HV activeregion. The first type HV device, in one embodiment, comprises a LDdevice, such as a LDMOS device. The HV device comprises a gate withfirst and second edges 179 a-b or sidewalls.

The gate includes a HV gate electrode 174 over a HV gate dielectric 172.The HV gate electrode, for example, comprises polysilicon. Other typesof HV gate electrode materials, such as polysilicide or metal silicide,are also useful. Various types of metal, such as cobalt, titanium ornickel, can be used. Other types of HV gate electrode materials may alsobe useful. Furthermore, the gate electrode may be doped with dopants.The HV gate electrode, for example, may be doped with the same dopanttype of the transistor type. Doping the HV gate electrode with otherdopant types is also useful. The HV gate dielectric can be siliconoxide. Other types of HV gate dielectric materials can also be useful.

In one embodiment, the material of the HV gate electrode and HV gatedielectric may depend on the CMOS process and/or technology. In oneembodiment, the material of the HV gate electrode and HV gate dielectricmay depend on the CMOS process for LV devices and/or technology. Forexample, cobalt silicide gate electrodes may be used for 0.18 μm and0.13 μm technologies while nickel silicide may be used for 0.09 μmtechnologies. Other configurations of gate electrode and gate dielectricmaterials are also useful.

Sidewalls of the gate can be provided with sidewall spacers 178. Thesidewall spacers, for example, comprise a dielectric material, such assilicon oxide, silicon nitride or a combination thereof. Other types ofmaterials can be used for the sidewall spacers.

In one embodiment, the various gate elements of the HV gate, such asgate electrode, gate dielectric and spacers are of the same type ofmaterial as the LV devices in the LV region. This facilitates processcompatibility for forming HV and LV devices.

The HV gate overlaps the channel and drift wells in the first and secondportions of the HV active region. A drift isolation region 180 a may beprovided within the drift well 136 on the high voltage side of the HVdevice. The drift isolation region 180 a can improve breakdown voltageof the HV device due to high voltage. For example, the drift isolationregion is particularly useful to sustain high voltages for applicationsbeyond about 10V. As shown, the drift isolation region 180 a is disposedin the drift well 136 under the gate. Disposing the drift well at otherpositions, such as partially underlying the gate may also useful.

A first type drain diffusion region 176 b is provided between the driftisolation region 180 a and isolation region 180 which isolates the HVactive region from other sub-active regions in the HV region. A firsttype source diffusion region 176 a is provided in the channel well 135of the first type HV active region. A source extension region 177 can beprovided which extends under the spacer on the channel side of the HVgate. The first type source and drain diffusion regions, for example,comprise a p-type diffusion regions for a p-type HV active region.Providing n-type diffusion regions for a n-type HV active region is alsouseful. The dopant depth and concentration of the diffusion regions maybe selected depending on the application. In one embodiment, the dopantdepth and concentration of diffusion regions may be the same as those ofLV devices. Other dopant depths and concentrations are also useful.

A second type body contact region 171 may be provided in the firstportion of the HV active region. As shown, the second type body contactregion 171 is between the source diffusion region 176 a and theisolation region 180. The second type body contact region comprisessecond type dopants. In one embodiment, dopant depth and concentrationof the body contact region may be the same as the diffusion regions ofthe LV devices. Other dopant depths and concentrations are also useful.The body contact region 171 provides electrical coupling to the channelwell 135.

An edge 133 of the channel well 135 extends below the gate on the sourceside of the gate. The edge 133, for example, can be referred to as thechannel edge of the channel well. The channel edge of the channel well135 and the first edge 179 a of the gate on the source side define achannel of the HV transistor having an effective channel length L.

The effective channel length, in one embodiment, is controlled by ionimplantation which is self-aligned to the gate edge. For example, dopantions are implanted using an implant mask through the gate electrode or ahard mask and the gate electrode. The implant mask is also used topattern the channel edge of the HV gate. The effective channel lengthmay be controlled by channel or body implant conditions selected tosatisfy threshold voltage and breakdown voltage requirements. Forexample, shorter effective channel length may be achieved by decreasingtilt angle, implant energy or dosage and vice-versa.

With the channel well being self-aligned to the gate edge of theimplant, process overlay issues are avoided. Very short effectivechannel lengths with very low Rds_(on) can be achieved, enabling highcurrent to pass through a small area. This is particularly useful fortechnologies beyond 0.35 μm, such as, for example, 0.25 μm, 0.18 μm and0.13 μm technologies.

Smaller area requirements for power management applications with reducedpower dissipation increases performance while reducing costs.

In one embodiment, the effective channel length L is less than 0.4 μm.In other embodiments, the effective channel length is less than 0.3 μm.In yet another embodiment, the effective channel length is less than0.25 μm. Other effective channel lengths may also be useful, forexample, depending on the application.

FIGS. 2 a-g show cross-sectional views of an embodiment of a process forforming a device or IC 100. Referring to FIG. 2 a, a substrate 101 isprovided. The substrate can comprise a silicon substrate, such as alightly p-type doped substrate. Other types of substrates, includingn-type doped substrates, silicon germanium or silicon-on-insulator(SOI), are also useful.

As shown, first and second device regions 110 and 160 are defined on thesubstrate. The first region, for example, comprises a LV device regionwhile the second region comprises a HV device region. Other types ofdevice regions or additional device regions may be provided.Alternatively, the device may include only a HV region.

The LV device region 110 can be defined with first and second typeactive sub-regions 112 and 116. In one embodiment, the first and secondtype active sub-regions are complementary type active sub-regions toform a complementary device such as a CMOS device. Formingnon-complementary or other types of devices is also useful.

As for the HV device region 160, a HV active region 165 is definedtherein. In one embodiment, the HV active region 165 can be a first orsecond type HV active region. Although only one HV active region isdepicted, it is understood that the HV device region may includeadditional HV active regions or sub-regions. The HV active sub-regionscan be complementary HV active sub-regions.

The substrate is also prepared with isolation regions 180 to separatethe device regions as well as other active device sub-regions. In oneembodiment, the isolation regions 180 comprise STIs. Variousconventional processes can be employed to form the STI regions. Forexample, the substrate can be etched using conventional etch and masktechniques to form trenches which are then filled with dielectricmaterials such as silicon oxide. Chemical mechanical polishing (CMP) canbe performed to remove the excess dielectric materials and provide aplanar substrate top surface. Other processes or materials can also beused to form the STIs.

In FIG. 2 b, the doped wells for the active regions of the deviceregions are formed. In one embodiment, a first type doped well 124 isformed in the second type LV active sub-region 116 and a second typedoped well 122 is formed in the first type LV active sub-region 112. Forexample, a n-type doped well is formed in the p-type active sub-regionand a p-type doped well is formed in the n-type active sub-region.

In the HV active region 165, it includes at least first and secondportions. For example, the first portion corresponds to a drain portionand the second portion corresponds to a source portion. In someembodiments, a third or middle portion is provided to separate the firstand second portions. Alternatively, the first and second portions arecontiguous portions without a middle portion.

In one embodiment, a doped well 136 is formed in the drain portion ofthe HV active region. The doped well, for example, is a drift well ofthe HV device. The drift well comprises the same type as the HV activeregion. In the case of a first type HV active region, the drift wellcomprises a first type. For example, a n-type drift well is provided fora n-type HV active region.

A drift STI region 180 a may be optionally provided in the drift well136. The drift STI region is disposed in the drift well to improvereliability of high voltage devices. For example, the drift STI regionimproves breakdown reliability of the HV device. The drift STI regioncan be formed at the same time as the other STI regions.

A deep HV well 132 may be provided in the HV active region 165. Asshown, the deep HV well 132 is formed in the whole HV active region 165and encompasses the first and second portions of the HV active region165. The deep HV well comprises an opposite type as the drift well andthe HV active region. In the case of a first type HV active region, thedeep well comprises a second type. For example, a p-type deep well isprovided for a n-type HV active region.

The depth and concentration of dopants of the various wells may dependon, for example, application. For example, higher voltage applicationsmay require lower doping concentration of dopants and greater depth ofthe wells. In one embodiment, the depth of the deep well 132 is about 3μm with a dopant concentration of about 5E16 cm⁻³. For the drift well136, it may have a depth of about 1.5 μm with a dopant concentration ofabout 5E17 cm⁻³. Other depths and dopant concentrations are also usefulfor the wells.

As described, the STI regions are formed prior to forming the variousdoped wells. Other process schemes, such as forming the STI regionsafter the various doped wells are formed may also be useful.

The doped wells can be formed by ion implantation. P-type dopants caninclude boron (B), BF₂ (boron compounded with fluorine), indium (In) ora combination thereof while n-type dopants can include phosphorus (P),arsenic (As), antimony (Sb) or a combination thereof. Generally, thefirst and second types of the active regions are formed selectively inseparate processes. For example, the n-type regions can be implantedwith n-type dopants while an implant mask prevents doping of the p-typeregions.

In one embodiment, the wells of the HV region are formed separately fromthe LV regions. For example, the LV wells can be formed first followedby the HV wells. Forming the HV wells prior to the LV wells is alsouseful. The different types of LV wells can be formed in separateprocesses and the different types of HV wells can also be formed inseparate processes. For example, the first type and second type wells inthe LV region are formed in separate implant processes. Similarly, thedifferent types of wells in the HV region are formed in separate implantprocesses.

A doped well can be formed by a single implant process or multipleimplant processes. In multiple implant processes, dopants can beimplanted at different energy levels to achieve the desired dopingprofiles. In the case of a single implant process, a high temperaturedrive-in process is performed to achieve the desired doping profile.

A single implant process may be employed to, for example, form deepwells. For a n-type deep well, phosphorus may be implanted with a dopantconcentration of about 6E12 cm⁻² at an energy level of about 2000 KeVfollowed by a two-hour drive-in at a temperature of about 1100° C.Single implant processes may also be used to form other types of wells.Forming wells using multiple implant processes may also be useful. Forexample, LV wells may be formed by multiple implant processes.

In FIG. 2 c, various layers of the gate are formed on the substrate. Inone embodiment, a gate dielectric layer 242 is formed over thesubstrate. The gate dielectric layer, for example, comprises siliconoxide. Other types of dielectric materials, such as silicon oxynitride,may also be useful. Alternatively, high-k, low-k or composite ofdielectric materials may be used. The thickness of the gate dielectriclayer 242 may be about 30 Å for 1.8V gate voltage transistors. Otherthicknesses may also be useful. The thickness, for example, may dependon the gate voltage applications. For example, higher gate voltages mayrequire thicker gate dielectric layers. In one embodiment, the gatedielectric layer is formed by thermal oxidation. Other techniques, suchas chemical vapor deposition (CVD), can also be used to form the gatedielectric layer.

A gate electrode layer 244 is deposited on the gate dielectric layer242. The gate electrode layer comprises, in one embodiment, polysilicon(poly). The gate electrode layer 244 can be formed as an amorphous ornon-amorphous layer. For amorphous deposited layer, subsequentprocessing can be performed to crystallize it. Other types of gateelectrode materials are also useful. For example, the polysilicon can besubsequently processed to form polysilicide or metal gates. Thethickness of the gate electrode layer may be about 2000 Å or less. Inanother embodiment, the thickness of the gate electrode layer is about2500 Å or less. In yet another embodiment, the thickness of the gateelectrode layer can be about 4000 Å or less. For example, in the case ofpolysilicide gates, the polysilicon may be about 2000 Å while thetungsten is about 2000 Å. Other thicknesses are also useful. Varioustechniques can be used to form the gate electrode layer. For example,polysilicon can be deposited by CVD while metal can be deposited bysputtering. Other techniques, depending on the material, may also beuseful.

Referring to FIG. 2 d, a mask layer 288 is formed on the substrate,covering the gate electrode layer. In one embodiment, the mask layercomprises photoresist. The mask is patterned as desired. To pattern themask layer, photolithography can be employed. For example, the mask canbe selectively exposed to an exposure source through a lithographicmask. Depending on whether a positive or negative resist is used, theexposed or unexposed portions are removed by development. To enhancelithographic resolution, an ARC layer (not shown) may be providedbeneath the mask layer.

The mask layer 288 is patterned to form an opening 289 to expose aportion of the gate electrode layer 244. In one embodiment, the openingcorresponds to the opening for the channel well implant. For example,the mask layer serves as the channel well implant mask. The ARC layermay be patterned with the mask layer. Subsequently patterning the ARClayer may also be useful.

In FIG. 2 e, the substrate is implanted with dopants to form a channelwell 135. In one embodiment, dopants of the opposite type as the type ofthe HV active region are implanted. For example, p-type dopants areimplanted into the p-type deep well of a n-type HV active region. In oneembodiment, the dopants are implanted at an angle to form a channel fromthe gate edge to the edge of the channel well. The implant angle θ canbe in a range of about 1 to 45°. Other implant angles may also beuseful. The implant conditions can be varied depending on applicationrequirements. For example, the angle, dose and energy can be selected toachieve the desired effective channel length.

In one embodiment, the channel well is formed by multiple implants. Forexample, the channel well can be formed by at least two tilt and rotateimplants. In one embodiment, the implant comprises a quad implant. Aquad implant comprises 4 tilted angled implants, each rotated by arotation angle. For example, a p-type channel well can be formed with aquad implant at a tilt angle of 30° with rotation angle of 45° with aboron dose of about 2E13 cm⁻² at an energy level of about 130 KeV. Othertilt angles, rotation angles, doses and energy levels are also useful.For example, a quad implant can comprise a tilt angle of 7° withrotation angle of 45° with a boron dose of about 2E13 cm⁻² at an energylevel of about 150 KeV.

After forming the channel doped well 135, exposed portions of the gateelectrode layer 244 are removed, as shown in FIG. 2 f. In oneembodiment, an anisotropic etch, such as a reactive ion etch (RIE) isperformed to remove exposed portions of the gate electrode layer. Theremoval of the exposed portions of the gate electrode layer, in oneembodiment, forms a first edge of a HV gate. The first edge, in oneembodiment, corresponds to the source side of the HV gate. As shown, thegate dielectric layer 242 serves as an etch stop for etching the gateelectrode layer. Leaving the gate dielectric layer can be advantageoussince it can serve as an implant mask for subsequent ion implantation toprotect the substrate from implant damage. Alternatively, the exposedportion of the gate dielectric layer can be removed. Removing the gatedielectric layer 242 to expose the substrate may also be useful. Afteretching the gate electrode layer, the mask layer 288 is removed.

As described, the implant mask, in one embodiment, serves as a channelwell implant mask as well as a mask for patterning the first edge (e.g.,source side) of the HV gate. By using the same mask to form the channelwell and source side of the gate, the channel is self-aligned to thegate edge. This enables the channel length of the HV device to be wellcontrolled to produce very short effective channel lengths to reduceRds_(on) performance. In one embodiment, the effective channel length Lis less than 0.4 μm. In other embodiments, the effective channel lengthis less than 0.3 μm. In yet another embodiment, the effective channellength is less than 0.25 μm.

Referring to FIG. 2 g, another mask layer 288 b is formed on thesubstrate and patterned. The mask layer is patterned to expose portionsof the gate electrode layer 244 to be removed, protecting portionscorresponding to gates of the LV devices. For example, the mask servesas a gate mask. Additionally, the mask layer 288 b protects the sourceportion of the HV region and the gate of the HV device. The exposedportions of the gate electrode layer 244 are removed to form gates ofboth the LV and HV devices.

After the gates are formed, the process continues to form the device, asillustrated in FIG. 1. The process, for example, includes formingextension regions 147 by ion implantation, followed by forming spacers148 and 178 and diffusion regions 146 and 176. The different types ofextension and diffusion regions can be formed in different processes.For example, n-type diffusion regions are formed in one implant processand p-type diffusion regions are formed in another process. Furthermore,the diffusion and extension regions of the different device regions canbe formed separately. Silicide gates and contacts can be formed afterthe diffusion regions are formed. For example, metals, such as cobaltare deposited on the substrate 101 and reacted to form silicide contactsand gates. The contacts and gates can be formed in the same or differentprocesses. Unreacted metals are removed. A pre-metal and an inter-leveldielectric layer can be formed in which contacts and interconnects areformed. Additional interconnect levels can be formed by, for example,dual damascene techniques. Final passivation, dicing, assembly andtesting may be performed to complete the IC.

An alternative embodiment of a process of forming a device 100 is shownin FIGS. 3 a-g. Referring to FIG. 3 a, a partially processed device isshown. The partially processed device is similar to that shown in FIG. 2c. A hard mask 388 is formed on the gate electrode layer 244. The hardmask, for example, comprises silicon oxide. In one embodiment, the hardmask 388 is formed by CVD. The thickness of the hard mask, for example,is about 40 nm. Other materials, techniques or thicknesses may also beuseful. For example, the hard mask may be formed from silicon nitride orother types of materials.

Referring to FIG. 3 b, a soft mask 287, such as photoresist, is formedon the hard mask 388. The soft mask can be patterned byphotolithographic techniques to form an opening 289 which can serve as achannel implant mask. An ARC layer can be provided between the soft mask287 and the hard mask 388. The pattern of the soft mask is transferredto the hard mask by, for example, RIE.

In one embodiment, the soft mask layer is removed after patterning ofthe hard mask, as shown in FIG. 3 c. The substrate is implanted withdopants to form a channel doped well 135. In one embodiment, dopants ofthe opposite type as the type of the HV active region are implanted. Forexample, p-type dopants are implanted into the p-type deep well of an-type HV active region.

In one embodiment, the dopants are implanted at an angle to form achannel from the gate edge to the edge of the channel well. The implantangle θ can be in a range of about 1 to 45°. Other implant angles mayalso be useful. The implant conditions can be varied depending onapplication requirements. For example, the angle, dose and energy can beselected to achieve the desired effective channel length.

In one embodiment, the channel well is formed by multiple implants. Forexample, the channel well can be formed by at least two tilt and rotateimplants. In one embodiment, the implant comprises a quad implant. Aquad implant comprises 4 tilted angled implants, each rotated by arotation angle. For example, a p-type channel well can be formed with aquad implant at a tilt angle of 30 with rotation angle of 45° with aboron dose of about 2E13 cm⁻² at an energy level of about 130 KeV. Othertilt angles, rotation angles, doses and energy levels are also useful.For example, a quad implant can comprise a tilt angle of 7° withrotation angle of 45° with a boron dose of about 2E13 cm⁻² at an energylevel of about 150 KeV.

As shown in FIG. 3 d, another soft mask layer 287 is deposited on thesubstrate, covering the hard mask layer and exposed gate electrodelayer. The soft mask is patterned by lithography. The soft mask protectsportions of the hard mask layer 388 corresponding to the transistorgates. A new ARC layer can be provided between the soft mask 287 and thehard mask 388. In FIG. 3 e, exposed portions of the hard mask areremoved, exposing portions of the gate electrode layer. Patterning ofthe hard mask layer can be achieved by, for example, RIE. The patternedhard mask serves as a gate mask. The soft mask, as shown in FIG. 3 f, isremoved after patterning the hard mask.

Referring to FIG. 3 g, the gate electrode layer 244 is patterned to formgates in the LV and HV region by, for example etch. Patterning of thegate electrode layer can be achieved using, for example, RIE. Thepatterning of the gate electrode layer also erodes the hard mask,reducing its thickness. The hard mask 388 can be removed by, forexample, a clean step after etching the gate electrode layer. Theprocess continues as previously described to complete the device.

The invention may be embodied in other specific forms without departingfrom the spirit or essential characteristics thereof. The foregoingembodiments, therefore, are to be considered in all respectsillustrative rather than limiting the invention described herein. Scopeof the invention is thus indicated by the appended claims, rather thanby the foregoing description, and all changes that come within themeaning and range of equivalency of the claims are intended to beembraced therein.

1. A method of forming a device comprising: providing a substrateprepared with an active device region, wherein the active device regionincludes gate stack layers of a gate stack comprising at least a gateelectrode layer over a gate dielectric layer; forming an implant mask onthe substrate with a mask opening exposing a portion of a top of thegate stack, the mask opening having first and second opposing edges;implanting ions through the mask opening and gate stack layers into thesubstrate to form a channel well in the substrate, wherein a firstchannel edge of the channel well extends beyond the first mask openingedge, wherein a first portion of the channel well is between the firstchannel edge and the first mask opening edge, the first portion definesa channel with a length L of a device; and wherein the channel of thedevice is disposed under a mask portion and a second portion of thechannel well is disposed below the mask opening.
 2. The method of claim1 wherein a top layer of the gate stack layers comprises the gateelectrode layer.
 3. The method of claim 2 wherein the gate electrodelayer comprises silicon, including amorphous or polysilicon.
 4. Themethod of claim 2 comprises: patterning the gate stack layers to form afirst gate edge of the gate stack; and further comprises patterning thegate stack layers to form a second gate edge of the gate stack afterforming the first gate edge.
 5. The method of claim 4 wherein the firstgate edge corresponds to a source edge of the gate of the device and thesecond gate edge corresponds to the drain edge of the gate of thedevice.
 6. The method of claim 1 further comprises patterning the gatestack to at least remove a portion of the gate electrode layer afterforming a first gate edge of the gate to form a second gate edge of thegate.
 7. The method of claim 6 wherein the first gate edge correspondsto a source edge of the gate of the device and the second gate edgecorresponds to the drain edge of the gate of the device.
 8. The methodof claim 1 wherein patterning the gate stack layers leaves the gatedielectric layer remaining on the substrate.
 9. The method of claim 1wherein: the gate stack layers comprise a hard mask layer over the gateelectrode layer; and patterning the hard mask using the implant mask toremove a portion of the hard mask layer to expose the gate electrodelayer; and implanting ions to form the channel well after patterning thehard mask.
 10. The method of claim 9 wherein the hard mask is furtherpatterned to serve as an etch mask of a gate.
 11. The method of claim 10further comprises patterning the gate stack layers with the patternedhard mask to form a gate with first and second gate edges.
 12. Themethod of claim 11 wherein patterning the gate stack layers leaves thegate dielectric layer remaining on the substrate.
 13. The method ofclaim 1 wherein implanting ions comprises a tilt angle implant.
 14. Themethod of claim 1 wherein a tilt angle of the implant is about 1-45°.15. The method of claim 1 wherein implanting ions comprises multipletilt angle implants which are rotated about a plane of the substrate.16. The method of claim 15 wherein a tilt angle of the implant is about1-45°.
 17. The method of claim 1 wherein implanting ions comprises aquad tilt angle implant which is rotated about a plane of the substrate.18. A method of forming a device comprising: providing a substrateprepared with an active device region which includes a doped drift wellin a first portion of the active device region and gate stack layers ofa gate stack comprising at least a gate electrode layer over a gatedielectric layer on the surface of the substrate; forming an implantmask on the substrate with a mask opening exposing a portion of a top ofthe gate stack, the mask opening having first and second opposing edges;implanting ions through the mask opening and gate stack layers into thesubstrate to form a channel well in the substrate, wherein a firstchannel edge of the channel well extends beyond the first mask openingedge, wherein a first portion of the channel well is between the firstchannel edge and the first mask opening edge, the first portion definesa channel with a length L of a device; and wherein the channel of thedevice is disposed under a mask portion and a second portion of thechannel well is disposed below the mask opening.
 19. The method of claim18 wherein the substrate comprises: a drift isolation region in thedoped drift well; and a doped deep well in the substrate of the activedevice region encompassing the doped drift well.
 20. A method of forminga device comprising: providing a substrate prepared with an activedevice region which includes a doped drift well in a first portion ofthe active device region and gate stack layers of a gate stackcomprising at least a gate electrode layer over a gate dielectric layeron the surface of the substrate; forming an implant mask on thesubstrate with a mask opening exposing a portion of a top of the gatestack, the mask opening having first and second opposing edges;implanting ions through the mask opening and gate stack layers into thesubstrate to form a channel well in the substrate in a second portion ofthe active region, wherein a first channel edge of the channel wellextends beyond the first mask opening edge, wherein a first portion ofthe channel well is between the first channel edge and the first maskopening edge, the first portion defines a channel with a length L of adevice; and wherein the channel of the device is disposed under a maskportion and a second portion of the channel well is disposed below themask opening.
 21. The method of claim 20 wherein the doped drift well inthe first portion of the active region is contiguous with the dopedchannel well in the second portion of the active region.
 22. The methodof claim 20 wherein the doped drift well in the first portion of theactive region is separated from the doped channel well in the secondportion of the active region by a third portion.